Ram

The Ri the MPl Page en MPU) is put (DBC by the M R/WB is byte at tl

Alternate -03 P.C. Boards (PROMs)

035131-02 J2

035132-02 N2

035137-02 K1

035138-02 N1

035133-02 H2

035134-02 M2

035153-02 K1

035151-02 H2

035139-02 J1

035140-02 M1

035154-02 J1

035135-02 F2

035136-02 L2

035152-02 F2

035141-02 H1

035142-02 L1

5155-02 L1

The NMI (non-maskable Interrupt) counter causes an interrupt Kt5t 1 —1

at the NMI input of the MPU every 4 msec. The interrupt is derived , , by dividing 3 KHz by a factor of 12 through counter C5. The inter- (¿X^X^Xt curs when pin 6 of inverter B5 goes tow. During power-up, the NMI counter is disabled by RESET. During Self-Test, the NMI is disabled by TEST.

FROM SWITCH INPUTS SHEET 2, SIDE B

ROM/PROM CIRCUITRY

Program Memory for the Asteroid tained in PROMs for the -01 version ROMs for the -02 version of the PCI equivalent to four PROMs. All PROM a common enable must be removed ing with a ROM. For example, rem locations F2, H1, L2 and L1 before ROM at location F1.

-Ol version

4-SV

LS04

AB9-A88-AB7 ■ ABfc-AB5-AB4 ■ AB3 . A 52 -ABI ^ ABHOBT DBfc ■ DBS ■ DB4-

LS04

IS

7Z 035131

NZ 035132

HI 035133

Mi 015.134

F2 03SIJ5

C£l it 03513b

N 1 035138

J i 03513»

M 1 035140

Ml 035141

A3 S A2 Al Ait

II

lb

17

1

2

3

4

1

b

5

W

04 03 OZ Ol CM

03 OZ 01

CiZ

12

12

13

1}

14

14

ctz

CEJ

ctz

CEZ

C£2

CEZ

C12

CEI

CEZ

CE2

PROMZ PROM I

PHOM0

[ denqiqs -change byjadica^c

denotes a test point

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