RAM is the temporary storage space for IPU and is enabled when_ZPAGE (Zero enable) is low. When R/WB (from the is low, the RAM stores the data byte in-)B0 thru DB7) at the location addressed j MPU address bus (ABO thru AB7). When is high, the MPU reads the stored data it the addressed location.

signal RAMSEL, when low, has the ef->f swapping pages 2 and 3 within the This allows greater programming flex-

035143-02 C1

035143-02 E/F2

035144-02 D/E1

035144-02 H2

035145-02 F1

035145-02 J2

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