41 Cpu Board

The control portion of the CPU Board is the Z-80 microprocessor. Basically, the Z-80 performs the following functions: It fetches an instruction, or command from a program memory and then executes that instruction. Usually, the processor fetches and executes instructions in a sequential manner and it does this quite rapidly. The ability to do tasks quickly is one of the two significant features of the microprocessor. The other feature is the ability to modify the order of program execution as a result of previous conditions. This "Decision Making" ability makes it extremely versatile.

Information in the form of instructions and data is contained in a "Program Memory" built up of seven type 2708 PROM's (refer to the CPU Schematic Diagram). These PBOM's are addressed by the Z-80's Address Bus. The information addressed is then applied to the Data Bus and input back to the Z-80 for processing. Occasionally, the Z-80 will have to store information in a temporary location and it uses the "Scratch Pad" RAM for this. Actually, there are two groups of RAM in the system, the Scratch Pad previously mentioned, and a Video RAM. The Video RAM will be discussed in a later section. For the present, it can be stated that both RAM's appear identical to the Z-80, except that they occupy different addresses.

Occasionally, the Z-80 has to access information outside of its normal sphere of influence such as the RAM's and PROM's. These "Outside World" events (coin switch closures, player movements, etc.) have to be acted upon. Also, the processor has to affect the "Outside World", such as flipping the picture or advancing the coin counter or turning on sounds at the appropriate time. These Input/Output (I/O) functions are treated differently than the normal Z-80 instructions. Any time the Z-80 attempts to access memory-whether to read a comnand (OPCODE FETCH) or to read a previously stored byte of data (MEMORY READ) or to store a data byte (MEMORY WRITE)-it brings its (MREQ*) pin true (a logical zero). On diagrams, a bar over the pin name implies that the function is true, or assertive, when it is at a logical zero. In the text, an asterisk replaces the bar (NOT function). The direction of data flow is signified by the RD* and WR* pins. An RD* implies that the processor is reading data and that the data is flowing from the addressed device to the processor. A WR* implies that the processor is writing data and that the data is flowing from the processor to the addressed device. When the processor is accessing a peripheral or Input/Output device, it asserts (brings true) its IORQ* (Input/Output Request) pin. A brief description of the pin definitions for the Z-80 microprocessor is provided in Table 4-1.

Both the Address and Data busses are buffered to enable then to drive the external chips of the system. The address bus, along with MREQ* and WR* are buffered by chips 1A, 2A and 3A. These chips are enabled by the inversion of BUSAK*. If the processor responds to a BUSRQ* signal, these chips will be turned off, or tri-stated. The data bus is buffered by a pair of bi-direct ional buffers. They are also turned off by the inversion of BUSAK*. The direction of the signal through the buffers is controlled by the WR* signal. Gating is provided to generate the signals IORD* (read From Input Port) and IOWR* (Write to Output Port). Gates are also used to buffer IORQ* and RFSH*. A crystal controlled oscillator composed of three inverters generates the CPU clock.






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