Timing Diagram Vertical Circuitry


An output bit on the I/O Sound Board is defined as the UPRIGHT*/FLIP bit and it implements a hardware inverstion of the video picture. This is accomplished by inverting or complementing the entire Video Address Bus. The net effect is to cause the counters to decrement from a maximum value, instead of incrementing from a minimum value. In other words, as far as the RAM is concerned, the counters are running backwards. The upper left hand corner of the screen is now FFFH, the upper right hand corner is FEOH, the lower left hand corner is 41FH and the lower right hand corner is 400H.

The hardware implementation of the flip is to connect all bits of the Video Address Bus to XOR gates 5D, 6D, 7D and 8D and to connect the outputs to the RAM Address Multiplexers. If the control input to the XOR's is a zero, the addresses are fed through unaffected. If the control input (the UPRIGHT/FLIP*) is a one, the addresses are inverted. Full Adder 7E compensates for the fact that the screen starts out at an address of 400H. (Since Address bit AB10 starts at a 1 for the beginning of the screen, it will become a zero through XOR gate 7D. Adder 7E adds a constant 1 (equivalent to 400H) to the top 3 bits of the Address bus to compensate, resulting in FFFH for the top left corner.

To implement a flipped image it is not adequate to merely complement the Ram Addresses. The resulting RAM data must also be shifted in reverse order. In addition, the color look up information must be flipped. This function is performed by two VideoShift Registers, one shifting from bit 0 through bit 7 (normal video) and the other shifting from bit 7 through bit 0 for flipped video. The color look up PROM is set up so the color data on the upper 3 output bits (for normal video) are reflected (or flipped) for the flipped video action. Multiplexer 5E selects the Video Shift Register as well as the set of color look up bits required for each condition.

4.2.5 Color Output. The serial Video stream generated by the selected Video Shift Register is gated with the output of the Color look up PROM (Chip 3E) to generate one of eight colors on the screen. The screen is divided into 896 color blocks with each block 8 pixels wide by 8 high. A pixel bit having a value of one (in any block) will be gated through to the monitor with the R, G, and B values given by the look-up PROM. A pixel of zero value will produce a black spot.

The addresses for Color look-up PFOM 3E come from Video Address bus bits ABO through AB4, which provide 32 horizontal areas. Bits AB8 through AB12 provide 32 (actually 28 due to the starting state of AB10 as described previously) vertical areas. For each area, a color bit value is selected with the value 0 (Black) through 7 (white). The D type flip-flops (6F and 7F) latch the color value every time the Video Shift Registers are loaded. Their outputs are then combined with the "RED SCREEN" signal.

During the game a "RED SCREEN" occurs whenever an enemy invader, or part of an invader's explosion, hits the player's base or tank. A "RED SCREEN" will also occur if the UFO reaches the bottom of the screen. This, along with an explosion sound, signifies the loss of a base. An output port on the I/O Sound Board results in the "RED SCREEN" signal. OR gate 7G will output a logic one under this condition (whether or not the actual color has red set). NAND gates

8F force the Green and Blue off. The outputs of the latter gates are combined with the inversion of serial video (provided by 8G) via OR gates 7G. If a color is to be displayed, the output of the OR gate will be zero. These signals are inverted by open-collector inverters 6G, and applied to the monitor at the 10-pin KK100 connector.

4.2.6 Miscellaneous Circuits. Power for the board is received through the Mother Board bus. The +5 Vdc power is used by all the circuits while -5 Vdc and +12 Vdc are required only by the color look up PROM. Although one output of the HBLANK* latch is connected to the BUSREQ* pin on the mother board, this feature is not operational since it is disconnected at the CPU Board.


The I/O Sound Board contains all the Input/Output interfaces of the system as well as all the sound generating circuitry. Refer to the schematic diagram at the end of this manual.

The actual interface to the processor is accomplished by the use of two 8255 Peripheral Interface Adapter's (PIA). As configured in Astro- Invaders, each PIA is used as either an input or output port but the PIA can actually be used as a bi-directional port with proper control signals.

All eight bits of the data bus connect to each PIA, as does AO, Al, IORD*, IOWR*, AND RESET. As explained in the CPU Board Theory-of-Operation paragraphs (4.1), Input/output ports are handled differently as compared to memory. When the CPU board atteirps to read an I/O port, it will bring IORD* true. Conversly, when an I/O write occurs, IOWR* is brought true. RESET initializes the PIA to a known state. Address bus bits AO and Al select registers internal to the PIA. Address bit A2 is used as a chip select (along with either IORD* or IOWR*) to the input PIA. Address bit A3 is the corresponding chip select to the output PIA. Processor addresses for the I/O ports are as follows:





4.3.1 Input Ports. PIA "A" (chip #20 on the I/O Sound Board) is the input Port. It receives information from the player switches, coin switch, etc. Inputs from all player controls are handled in like manner and, therefore, only one of eight identical circuits will be explained. All player controls provide switch closures to ground. When closure occurs, a 3.3 microfarad capacitor is discharged through a 100 Ohm Resistor in series with the switch. When the voltage level on the capacitor drops below the low going threshold of the 74LS14, (approximately one volt) the 74LS14 output will switch to a logical one. The CPU constantly monitors the input ports (as a result of its interrupt routine) and will respond according to which switch is closed. When the switch opens, the capacitor is recharged through the 100 ohm and a 1000 ohm resistor to the +5 volt supply. When the charge across the capacitor reaches the high going threshold of 74LS14, (approximately two volts) its output will switch to a logical zero.

The processor is now aware of the fact that the switch is open, and ceases its response. The game setting switches simply apply either a logical one or zero to the input port bit. A pull-up resistor is provided to insure a logical one when the switch is open.

The coin switch operates in a similar manner and uses a similar R-C debounce circuit. The output of the debounce circuit is connected to a driver transistor used to advance the coin counter. This output is available on pin 8 of the Input/Output connector. An anti-kickback diode is also mounted on the board. It's anode is connected to the counter output transistor collector. The cathode is connected to pin 6 of the same connector. The debounce circuit output is also connected to the « clear input of a 74LS123 one-shot. This one-shot is used as a pulse stretcher to insure that the processor is made aware of a coin drop. When the debounce circuit output goes to a logical one, (as explained above), the clear signal is removed from the one-shot, causing it to start a timing cycle. This timing cycle will last for approximately 28 milliseconds during which time the Q output will be a logical zero. This output is combined with the service switch input at NAND gate 18 and the result is applied to port A, bit 0, of the input port. The service switch will add credit but will not advance the coin counter.

4.3.2 Output Ports. All bits of each output port are used for sound generation except for port 8, bit 5, which is used as the UPRIGHT*/FLIP control bit. Its output is inverted, then applied to the game cabinet jumper select. If the connection between the inverter and the edge connector (Pin 41) is broken, and the edge connector grounded, the game is set up as an upright, and the picture will not flip between players. Conversely, if the connection is not broken, the picture will flip between players.

Port A, output bit 2 controls the missile explosion sound. It is also connected to the bus connector (pin 23), and becomes the RED SCREEN control bit. When this sound effect is generated, the screen turns red. See paragraph 4.2.5 for details.

4.3.3 Fire And Tank Explosion Sound Generation. The"Fire" and "Tank Explosion" sounds are generated in a similar manner since they both use a noise generator consisting of an oscillator made up of two 74C86 XQR gates (chip #4) which clock a CMOS 4006 Shift Register. Two outputs of the shift register, Q17 and Q19, are combined in an XOR gate and fed back to the input, D5. The shift register and XOR feedback make up a psuedo-randean noise generator. A network made up of a O.luF capacitor, two diodes and two resistors (1 MEG and 270K ohm) insure that the shift register does not come up in an illegal state (e.g., all Q's at zero). One of the shift register taps (Q13) is used as the output of the noise generator and is input to both the Fire sound generator and the Tank Explosion sound generator.

The control circuitry for the Fire sound generator, the Tank explosion sound generator and the "Invader Destroyed" sound use similar circuits. Any one of these circuits operates as follows: The output bit of PIA B connects to an open-collector buffer (type 7407). Normally, the buffer output is on, which disables the sound generation. When the PIA Output Bit is written to a one, the buffer turns off, enabling the sound. A IK ohm pull-up resistor at the buffer output provides a one-going signal which is differentiated by the following R-C network. This provides a positive going pulse to the non-inverting input of an OP-Amp (chip 9 for both generators). The OP-Amp output now goes positive, which is fed back by a 1 megohm resistor to the non-inverting input. This "Hysteresis" action has a latching effect, holding the output high. The high going output also charges a timing capacitor connected to the Op- Amp's inverting input through a 560K ohm feedback resistor. The capacitor value and the associated bias network determine the time constant of the circuit. When the capacitor charges to the voltage on the non-inverting input of the Op-Amp, its output returns low, discharging the capacitor. This circuit is then a triggered one-shot, whose time constant is determined by the capacitor and biasing network.

In the case of the Tank Explosion Sound, the output of the one-shot is put through a diode, resistor and capacitor and applied to pin 10 of Op- Amp 9. The output of this network (as applied to pin 10) will go to a logic one at the time of the one-shot output, and will decay off to a zero when the one-shot output goes back to zero. This envelope is applied to Op-Amp 9, which sums it together with the output of the noise generator. The Op-Amp output is a low-pass, filtered signal which is applied to Sound Adjust Potentiometer VRl.

The output of the "Fire" sound one-shot (also chip 9) is applied to a short-time envelope generator made up of Norton-Amp 10. Its output is much the same as the diode, capacitor and resistor network mentioned earlier, but has a shorter time duration. Other Norton amplifiers in chip 10 wave shape and amplify the output of the noise generator. This output together with the decaying Norton Amp output envelope is applied to a summing amplifier (Norton Amp 10, Pins 2, 3 and 4). This decaying, filtered noise envelope is applied to Op-Amp 9 at pin 6 together with another decaying envelope (originating at the Fire sound 7407 buffer and applied through a diode, capacitor and resistor network to pin 5). The signals at pins 5 and 6 are summed together and the output (pin 7) is a high-pass, filtered signal that is applied to Sound Adjust Potentiometer VR2.

4.3.4 Invader-Destroyed And UFO Sound Generation. The basis of the invader-destroyed and UFO sounds is a Voltage Controlled Oscillator, or Sweep oscillator, made up of Op-Amp 6 (pins 1, 2 and 3) and Norton-Amp 5. The Op-Amp generates triggers to initiate a sawtooth waveform generated by the Norton-Amp (pins 10, 11 and 12). This sawtooth is then applied to pins 1, 6 and 5 of chip 5. This stage, along with the stage using pins 2, 3 and 4, plus a transistor, forms the actual oscillator circuit. The frequency of oscillation is determined by the sawtooth waveform voltage and the transistor. When the output voltage at chip 5, pin 5, reaches a value determined by the biasing of chip 5 pins 2, 3 and 4, the transistor is turned on which results in a negative going ramp at pin 5. When the sawtooth voltage is reached, the transistor turns off, and the ramp starts to go positive again. The output at pin 5 of chip 5, is applied to the "Invader Destroyed" and "UFO" sound generators.

The Invader Destroyed Control circuit (through a 7407 buffer, pins 12 and 13) is the same type of triggered one-shot as explained previously for the Fire sound except that the time constant has been altered. The output is connected to a triangle generator (chip 5 pins 8, 9 and 13), the output envelope of which is summed together with the VCO output by chip 6 pins 5, 6 and 7. The output signal is a high-pass filtered version applied to potentiometer VR4. The UFO sound is normally disabled by a conducting transistor which shorts the sound to ground. Isolation between this circuit and the voltage controlled oscillator (VCO) is provided by a 22K ohm resistor. When the processor writes output port A bit 0 to a one, the inversion provided by the 74LS14 (chip 14) turns the transistor off. The VCO output can now pass through the high-pass filter and be applied to sound adjusting potentiometer VR5.

4.3.5 UPO-Destroyed Sound. The control circuit for this sound uses a 7407 open-collector buffer (pins 5 and 6) to start and stop a triangle generator (chip 7 pins 8, 9 and 13). The output of this triangle generator is applied to Summer chip 8 pins 1, 2 and 3. Another VCO is made up of chip 7 (pins 2, 3, 4; 1, 5, 6; 10, 11, 12), chip 8 (pins 12, 13 and 14) and a transistor. This VCO operates in like manner to the UFO sound generator, except that the time constants are charged to vary the frequency and sweep rate. The UFO-destroyed VCO output is also applied to the Summer circuit (chip 8 pin 2). The Summer output is high- pass filtered, and applied to Sound Adjusting Potentiometer VR3.

4.3.6 Invaders-Advancing And Bonus Sound. The "Invaders-Advancing" sound is generated by one half of a 556 (chip 11) dual timer. The timer is set up as a standard astable multivibrator, except that the charge time constant is variable as controlled by PIA B. The discharge time constant is fixed by the 75K ohm resistor between pins 12 and 13 of the chip. PIA output Port-B, Bits 0 through 3 control the charge time by switching in various resistor values to the +5 volt supply. Four open-collector buffers (7407, chip 15) isolate the pulled-up resistors from the PIA, while diodes isolate the pulled-down (or switched out) resistors from the 556. Sixteen possible charge rates are provided by enabling various combinations of the four circuits. The output of the 556 is buffered by gate 3 (a 7411), band-pass filtered and applied to setting pot VR6.

The Bonus sound is generated by the other section of the 556 dual timer in conjunction with a 555 timer. Both timers are configured as astable multivibrators, but with different repetition rates. PIA Port B bit 4 enables this section of the 556 by removing the logical zero from reset pin 4. The 555 (chip 13) free-runs. The enable line (Port B bit 4), the 556 output and the 555 output are combined in AND gate 13. The output is buffered by another AND gate (chip 13), high pass filtered, and applied to sound setting potentiometer VR7. AND gate 3 (pin 12) will be a a logic one only when both oscillator outputs and the enable are at logic ones.

4.3.7 Audio Summer And Power Amplifier. The slider of each VR potentiometer (mentioned in previous descriptions) is connected to a common point through 22K ohm resistors and a 1 microfarad capacitor. This common point is the inverting input of Op-Amp 2 (pins 1, 2 and 3). Potentiometer VR8, in the feedback circuit of the Op-Amp, sets the master volume. The output of this amplifier feeds one input of a Power Amplifier (chip 1 pin 7). An inverting Op-Amp (chip 2 pins 12, 13 and 14) feeds the signal to the other Power Amplifier input.

A sound enable control is implemented by chip 15 (a 7407), a pull—up resistor, and two diodes which connect to the inverting inputs of both Op- Amps. Any time the buffer chip produces a logic zero at its output, the inverting

Op-Amps and hence the Power Amplifier are enabled. When the 7407 is off, the pull-up resistor and diodes swamp the Op-Amp inputs, taking their outputs low. The open-collector buffer is controlled by a NAND gate (chip 18). One of its inputs is connected to an R-C network that forces the NAND gate output high for a period of time when power is first applied to the game. This mutes, or turns off the Power Amplifier. After the capacitor has charged, the processor may enable or disable sounds by writing bit 5 of output Port A to a logic one or a zero, respectively. Each output of the Power Amplifier is connected to one terminal of the speaker to form a bridge configuration. The inverting stage provided by Op-Amp 2 (pins 1, 2, 7, 3 and 14) forces the amplifier outputs to be out of phase by 180 degrees, causing one side of the speaker to be driven high, while the other side is driven low.

4.3.8 Power Requirements. The two 8255 PIA's, the 7407's, the 555, 556, 74IS14's, 74123, 7411 and 74LS00 are supplied by the +5 volt regulated supply as distributed via the Mother Board interconnection busses: All other circuitry, with the exception of the Power Amplifier itself, is driven from the +12 Volt regulated supply as distributed via the Mother Board interconnecting busses. The Power Amplifier receives power from the VAUDIO (+15 max.) supply, brought in through the I/O Sound Board edge connector.

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