3.4.1 General Comments:
This subsection gives a technical description of the game's electronic circuitry. Drawing number 005629 is a nine-sheet schematic diagram of the circuitry on the printed circuit board, and drawing number A005629 is the PCB assembly drawing showing the locations of the components called out on the schematic. The position of each integrated circuit device is identified by a column letter designation (A through R), and by a row numberdesignation (1 through 9). Drawing number 005816 is a schematic of the harness wiring inside the game cabinet. These drawings and a schematic diagram of the TV monitor's circuitry are included in Section VII of this manual.
On the PCB schematic the symbol P (appearing at various inputs to logic gates and other integrated circuits) indicates a connection to + 5 volts through a pull-up resistor.
In the subparagraphs that follow, the portions of the circuitry being described can be located on the PCB schematic by finding the intersection of the zone letters (A, B, C or D) and the zone numbers (1 through 8). For example, the designation Sheet 1, Zone A 8 refers to the extreme lower left corner of sheet 1 of the schematic.
Sheet 9 of the PCB schematic is a detailed block diagram of the board's circuitry. The main data and control interconnections between the blocks, as well as those coming from the front panel joysticks and switches, are also shown on the diagram.
This subsection of the manual gives technical descriptions of game circuitry regarded as field-repairable, Correction in the field of problems traced to certain portions of the circuitry on the game's PCB may require replacement of the entire board.
3.4.2 Sheet 6 of Schematic:
(a) Clock Generator (Zone D7 & D8). The output of a 12-MHz crystal-controlled oscillator drives flip-flop L1 to produce the H CLOCK signal at LI pin 5. This signal provides the basic clock synchronization for the game circuitry and also drives the horizontal countdown chain.
(b) Horizontal and Vertical Countdown Chains (Remainder of Sheet). Flip-flop L1 and counters R1 and PI form a countdown chain that counts down the frequency of the H CLOCK signal to produce the 1H through 256H timing signals. Certain of these signals are applied to flip-flop N2 to produce the H SYNC signal whose timing forms the basis for the horizontal synchronization information sent to the TV monitor on the composite video signal.
The H SYNC signal ¡5 also applied to counters A3 and B3 and flip-flop D2 and N2, which form the vertical countdown chain. These counters produce the 1V through 128V timing signals. Also flip-flop N2 produces the V RESET signal that changes state once per picture frame. Counter R8 (in Zone B2) produces a signal whose timing forms the basis for the vertical synchronization information sent to the TV monitor,
(c) Video Summing (Zone C2). The junction of resistors R44 through R48 forms the video summing point for the various signals that are combined on the composite video sent to the TV monitor. The timing of the PLAYFIELD signal, coupled through R45, determines when a picture is produced on the TV screen. The synchronization information is coupled through R46. The ball portion of the TV picture is coupled through R47, the pitcher figure through R48, and the remaining playfield objects through R44.
3.4.3 Sheet 1 of Schematic:
(a) joystick Interface (Zones B, C, D 7 and 8). The eight potentiometers on the PCB are adjusted at the factory and none of the settings should be disturbed after the game arrives at the game site. (Only potentiometers on the joystick assemblies should be adjusted at the game site.) A wire from each joystick potentiometer connects to the negative input of a type-LM339 amplifier.
(b) Ramp Generator (Zones A 6, 7, 8). Flip-flop P7 drives a 2N3643 transistor that has a large resistor-capacitor load connected to its collector terminal. The timing of the flip-flop's output causes a ramp-shaped waveform to appear at the positive inputs to the LM339 amplifiers in location L8. Five ramps are developed during one picture frame time on the TV monitor.
(c) Pot-Ramp Comparators (Zones B6, C6, D6). The amplifiers in L8 form four position-sensing circuits, as follows: vertical (up/down) and horizontal (right/left) circuits for the right player's joystick position, and a similar pair for the left player's joystick position. The output of each LM339 amplifier will be either low or high. The output changes from low to high at the time that the ramp waveform crosses the voltage that is applied from the joysticks (at L8 pins 6, 4, 10 and 8). Note that each of the four comparators can change state independently of one another.
(d) Pol Interrupt Disables (Zones B5, C5, D5) and Pot Interrupt (Zone C4). At the beginning of a ramp waveform the gates 17 will be open, so that the comparator outputs can pass through the gates and on to gate K6. If any of the signals applied to gate K6 go low, then the output at K6 pin 6 will go high. This signal, along with the ramp timing signal and H SYNC, is applied to gate P2. With this arrangement the IRQ (interrupt lequest) signal, at gale P2 pin 12, can only be produced during H SYNC time once every line on the TV. Therefore the first comparator to indicate that the ramp has crossed the voltage will be the one to cause the first interrupt to be produced.
(e) Interrupt fvenf Time Data (Zones D4 and B4). When the game's control circuitry receives the interrupt request signal, a READS POTS command is sent to pin 1 of the type-8T98 tri-state buffer in location L6. When a low is applied at pin 1, all four of the gates in the 8T98 will be energized. The DO through D3 outputs are then interrogated to determine which comparator has caused the interrupt.
After this has been done, the control circuitry shuts off the READS POTS signal and a READ VERT (read vertical) command is produced. A low is applied to pins 1 and 15 of the type-8T97 buffer device in location A4. Now the six timing signals 1V through 32V are passed through and on to the DO through D5 output lines. This timing allows the control circuitry to determine when the interrupt occurred.
As the last step in the interrogation sequence the control circuitry must close gate L7 to block off the appropriate comparator(s). This is done by means of the DO through D3 commands which cause the flip-flops in location K7 to be set, thus shutting off gates L7 (at pins 2, or 5, or 12, or 9). All the flip-flops are reset before the start of each new ramp waveform.
3.4.4 Sheet 2 of Schematic:
fa,) X-Y Coordinate Generators (left half of schematic). For the ball, the counters K4 and D4 produce the horizontal component of its position on the screen, and J4 and E4 produce the vertical component. Likewise, for the pitcher figure, counters L4 and C4 produce the horizontal component of the figure's position, and H4 and F4 produce the vertical component. These are four sets of divide-by-256 counters that are preset at a particular time during the play sequence. The preset information is contained on the eight signal lines DO through D7, and the presetting is done during vertical blanking time.
The ball contribution to the picture is contained in the BALL VIDEO signal produced at P8 pin 12. The outputs from the counters for the pitcher figure connect to two PROM devices in locations E2 and F2, and to a type-74175 device in location F3.
(b) Graphics Select and Video Shift Register (right half of schematic). The type-74175 device in location F3 determines which of the pitcher pictures will be selected out of the PROMs. The PROMs have 16 pictures, all for the pitcher only. The type-75166 devices In locations E1 and H1 form a serial shift register. The parallel input data to this shift register come from the PROMs. The shift register is bidirectional; it can shift left or shift right. The output from the shift register produces the pitcher contribution to the TV picture, at P8 pin 10.
3.4.5 Sheet 3 of Schematic:
(a) PI ay field Rams (left half of sheet). The type-2111 RAMs in locations L3, P3, M3 and N3 produce graphics address data that are applied to the playfield ROM or ROMs shown on sheet 4. The address data applied to the RAMs, in turn, are produced by the two type-74157 devices in locations R3 and K3, The RAMs produce addresses for 512 picture "blocks" (each 8 dots wide by 16 dots high) on the TV screen. But the actual graphics (letters, numerals, baselines, runner figures, etc.), however, are stored in the playfield ROM.
(b) Video Shift Register (right half of sheet). The type-74194 devices form a bidirectional shift register. The outputs from the playfiold ROM or ROMs are applied in parallel to this shift register. The playfield objects picture information in serialized form is contained in the VIDEO OUT signal, produced at N7 pin 8. The PLAYFIELD signal contains the timing that determines when the picture will appear on the TV screen,
3.4.6 Sheet 4 of Schematic:
Playfield ROMs (left half of sheet) and Playfield ROM (right half of sheet). The page's printed circuit board is designed so that either four ROM devices—in locations J2, L2, K2 and M2—or else one type-4600 ROM device can be installed on the board. (A board will be built with one choice or the other, but not both choices simultaneously.) The operation of the game is the same under either choice. The ROM circuit function has already been covered in subparagraph 3.4.5.
3.4.7 Sheet 5 of Schematic:
(a) Buffers For On-Board Mode Switches and Front Panel Switches (Zone C & D 6, 7, 8). The switches contained in the structuring switch assembly mounted on the game's PCB, the switches on the front pane) that are operated by the players, and the two coin mechanism switches all connect to the type-8T97 buffer devices in locations K8 and H8. These buffersproduce the buffered data, the signals DO through D7.
(b) Came Address Decode (right half of sheet). The type-7442 devices in locations H3 and M6 are used as decoders that produce the various control signals needed during a play sequence. The type-9334 device in location F7 is used as an addressable latch that produces the control signals used in the sound generation circuitry. This latch also produces a signal that turns on an SCR to provide the lamp current when the TWO PLAYER START push button is to be backlighted.
3.4.8 Sheet 7 of Schematic:
(a) Random Noise Generator (Zones D7 through 8). The type-74164 devices in locations B7 and C7, and flip-flop D7 and gates E7, form a digital noise generator. Clocking for this circuit is provided by the 128V and 256H timing signals produced by the countdown chains (see (b) of subparagraph 3.4.2). The noise output signal is produced at D7 pin 8.
(b) Bat Sound (Zones C7 & C8). The type-556 device in location £8 forms a circuit that produces two short, gated square waves. These signals arc slightly offset in frequency, and interact together during the sound summing to give a sharp cracking sound when the ball hits the bat. The circuit is triggered by the BAT HIT ON/OFF signal.
(c.) Crowd Roar (Zone CS). The type-LM741 amplifier in location D8 is connected as a bandpass filter. It takes the output signal from the random noise generator and makes it seem more like a crowd roar sound.
(d) Footstep Generator (Zone 84). The amplifier in location C8 acts as a current-controlled volume control circuit. Its output gets louder as the resistance from C8 pin 2 to ground is lowered. The circuit is driven by the FOOTSTEP OFF/ON signal, so that footstep sounds are produced whenever any runner is advancing toward a base or home plate.
(c) Crowd Volume Control (Zones C3 & C4). The amplifier in location A8 also acts a current-controlled volume control. The three control signals CROWD VERY LOUD, CROWD OFF/ON and CROWD SOFT LOUD vary the resistance from A8 pin 2 to ground, so that the three amplitude levels of the crowd roar sound are heard during a play sequence.
(f) Master Volume Control and Output Amplifier (Zones A through D 7 & 2). Potentiometer R95 is connected to the sound summing point and provides the speaker volume adjustment described in paragraph 5.3 in Section V of this manual. The output amplifier drives the speaker mounted in the upper portion of the cabinet, above the TV monitor.
(g) Power Supply (Zones A, 66 through 8). The amplifier is connected in a full-wave diode rectifier circuit that provides the +5 volt supply for the board. A second pair of diodes is connected in a full-wave circuit that produces an unregulated +18 volts for the speaker amplifier circuit.
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