The AY processor system (module) consists of T3 (CPU), S3 (data bus driver), N3 (ROM), K3 (ROM), H3 (RAM), E3, G3, N4, S5 (output ports), B3 (input port), A3 (input code latch), T4 and half of S2 (decoders). The processor, T3, receives its interrupts from its input latch system, A3 and A4, and NMI
(non-maskable interrupt) from the output of the programmable timer, G4 pin 8.
Jumpers JP1 and JP2 at RAM H3, pin 19, allow for different types of RAM. When a HM6116 or 2158A RAM is used, JP1 is connected. When a 2158B is used, JP2 is connected.
The address decoder (T4) uses A13 through A15 to divide the memory map into 8K boundries. Address lines All and A12 are also split into 4 by half of S2. This produces eleven active low chip enable signals.
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