The DAC processor system (module) consists of N1 (CPU), N2 (data bus driver), K2 (ROM), H2 (RAM), E2 (dual DAC), B2 (input code latch) and half of S2 (decoder). The CPU receives the interrupt from the input latch system (A3, A4) and the NMI (nonmaskable interrupt) from S2, pin 10, of the AY processor.
The two jumpers, JP3 and JP4, allow for different types of RAM. For use of HM6116 or 2158A type RAM, JP3 should be connected and JP4 open. If using a 2158B RAM, the opposite applies.
The memory map is split into four 16K boundries by S2, using address lines A14 and A15. These signals are used to select each RAM, ROM, DAC or input port device.
E2 is the Dual Digital to Analog Converter. DAC A is used for a 256 position volume control. It uses +5V DC for a reference voltage and has an op amp (B1 pins 5, 6 and 7)for current to voltage conversion. The output of DAC A at B1 pin 7 should swing between zero and -5V DC, depending on the current converted voltage from DAC A. DAC B's output at B1 pin 8 should swing between zero and +5V DC, depending on the sound being produced. This signal output is capacitively coupled by C13 and sent to the main summer.
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