Frame Number Decoder

The 24-bit Phillips Frame Number Code is stripped from the video and is received at TTL levels from the Color/Sync Board on J7. The frame number code is squared up and inverted by A2 [Schmitt inverter). This signal is sent to a network of C29, R30 and A2 (positive edge detector), an inverter and another positive edge detector. These voltage spikes are summed by A4 (NAND gate) so that U5 can strip the clock of the frame data. The positive and negative edge voltage spikes are also inverted by A3 and summed with the clock to set up Set and Reset pulses for the D flip flop (B3). The D flip flop strips the data from the frame number signal for the shift registers B1, G1 and HI. The four input NAND gate detects a valid frame number and produces the clocking signal that latches the frame number into the latches B2,G2 and H2. The frame number is then read into the game machine via the data bus and strobes IP5, IP6 and IP7.

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