7

Negative Flag

3.2.5 Program Counter

The program counter contains the 16-bit address of the next instruction to be executed by the microprocessor. It i3 automatically updated after the execution of each instruction.

3.3 Format of 6502 instructions

All 6502 instructions consist of one, two, or three bytes. The first byte of the instruction (called the "opcode") tells the 6502

1. What operation is to be performed.

2. How may byte3 are in the instruction (i.e. one, two, or three).

3. What the additional bytes in the instruction are to be used for.

The possible operations that can be performed by 6502 Instructions will be given when the Instruction set is described in Section 3« H. The second and third items In this list are collectively referred to as the "addressing mode" and will now be discussed in more detail.

The 6502 microprocessor recognizes thirteen different addressing modes. Two of the addressing modes tell the 6502 that the only byte in the instruction i3 the opcode. One of the addressing modes tells the 6502 that there are two bytes in the Instruction and that the second byte contains the actual data to be used in performing the requested operation. For all other addressing modes, the one or two bytes following the opcode are used by the 6502 to calculate a "targot address" for the Instruction.

The exact manner in which the target address is calculated depends on the particular addressing mode selected. A description of the target address calculation is included as part of the description of each addressing mode given in Sections 3.3-1 to 3-3-12. The use that is made of the target address depends on the operation being performed. For example:

If the instruction is a register load operation, the target address specifies the address in memory whose contents i3 to be loaded into the register.

If the instruction is a register store operation, the target specifies the address in memory into which the value in the register i3 to be stored.

If the instruction 13 a jump operation, the target address specifies to what address the microprocessor is to Jump.

Many operations can be combined with more than one addre33ing mode. For example, consider the operation that shifts a byte of data one bit to the left. Using one of the possible 6502 addressing modes for this instruction, you can specify the 16-bit address of the data byte that is to be shifted. Alternatively, by specifying a different addressing mode, you can shift a data byte that is in the accumulator.

It is important to note that not all operations can be combined with all addressing modes (i.e., no opcode exists for many imaginable combinations of operations and addressing modes). Until you are familiar with the 6502, you will have to take care to insure that a program you are writing does not depend crucially on a very reasonable (but nonexistent!) operation and addressing mode combination.

All the addressing modes used by the 6502 are described below. The abbreviations for the addressing modes used by the MagiCard instruction dump feature (see Section '1.3) are shown within square brackets.

3-3-1 [ 1 "Accumulator" addressing mode or "Implied" addressing mode: Total instruction length is one byte. Accumulator addressing mean3 that the accumulator contains the operand (data to be used by the instruction). Implied addressing means that the operand i3 implied by the operation itself.

3.3*2 [I] "Immediate" addressing mode:

Total instruction length is two bytes. The second byte of the instruction is the actual value of the operand. Another way to think of this is that the target addre33 for the operation 13 the address of the 3econd byte of the instruction.

Total instruction length is three bytes. The second and third bytes of the instruction contain the target address for the operation. The second byte of the instruction contains the least significant eight bits of the address, and the third byte of the instruction contains the mo3t significant eight bits of the address.

Total instruction length i3 two bytes. The second byte of the instruction contains the target address. This mode is similar to the absolute addressing mode except only addresses from 00 to FF may be referenced.

3.3.5 [ZX] "Zero Page X Indexed" addressing mode:

Total instruction length is two bytes. The target address is found by adding the second byte of the instruction to the contents of the X index register (only the lower eight bits of the sum are kept).

3.3.6 [ZY] "Zero Page Y Indexed" addressing mode:

The same as zero page X indexed except the Y index register is used. Note: this mode is available for only two instructions—load X index register (LDX) and store X index register (STX).

3-3-7 TX] "Absolute X Indexed" addressing mode:

Total instruction length is three byte3. The second and third bytes of the instruction contain a sixteen-bit address in the same manner as in absolute addressing. The target address is found by adding the contents of the X index register to this 3ixteen-bit address. (Note: The addition of the X index register to the original sixteen-bit address is performed in a sixteen-bit manner. For example, if tho second and third bytes of the instruction wore C9 and FA, and the contents of the X index register were 40, then the target address would be FAC9 ♦ 40 = FB09)

3«3«8 [Y] "Absolute Y Indexed" addressing mode.

This mode is the same as absolute X indexed mode except the Y index register is used. (Note: This mode i3 available for fewer instructions than "Absolute X Indexed" mode.)

3.3*9 [X)] "Indirect X" addressing mode.

Total instruction length is two bytes. The second byte of this instruction is added to the contents of the X index register to form an eight-bit address (as in the [ZX] addressing mode). The contents of this eight-bit address and the address Immediately following are then taken to be the target address.

For example, assume that the second byte of an [X)] instruction is 80 and the contents of the X index register i3 3. The contents of memory location 83 contain the lower eight bit3 of the target addres3, and the contents of memory location 84 contain the upper eight bits of the target address.

3.3.10 [)Y] "Indirect Y" addressing mode.

Total instruction length is two bytes. The second byte of the Instruction contains an eight-bit address. The contents of this address and the following address are taken as a sixteen-bit address (the least significant byte of the sixteen-bit address Is in the fir3t byte as in [A]). The target address is formed by adding the contents of the Y index register to the 3lxteen-bit address.

For example, assume that the 3econd byte of a [)Y] instruction is

80 and the contents of the Y index register is 2. The 6502 first forms a sixteen-blt address by getting its lower eight bits from location 80 (which we will assume contains FF) and its upper eight bits from location 81 (which we will assume contains F0). The contents of the Y index register (3) 13 then added to the 3ixteen-bit address (FCrF) resulting in a target addre33 of F102.

It is very important not to confuse [)Y] addressing with [X)] addressing. In practice, [)Y] is used more often and should be understood completely. The [X)] mode 13 often used with zero in the X index register.

3.3.11 [()] "Absolute Indirect" addressing mode.

Total instruction length is three bytes. The second and third bytes of the instruction contain a sixteen-bit address (the lower eight bits are in the second byte, and the upper eight bits are in the third byte). The location at this address contains the lower eight bits of the target address. The upper eight bits of the target address are in the next memory location. (Note: This mode is only used by the JMP (Jump) Instruction).

3-3.12 [nn] "Relative" addressing mode.

Total instruction length is two bytes. The second byte of the instruction is treated a3 a signed two's-complement number (i.e., FF = -1, FE = -2, ..., 80 = -80, 7F = +7F, ...). This signed number is added to the sixteen-bit address of the fir3t byte of the next instruction and the result is the target address. For example, assume that the two bytes of an Instruction that uses relative addressing are contained in memory locations F311 and F312. Further, assume that the second byte of the instruction contains FD. The target address Tor the instruction is FD ♦ F313 = -3 ♦ F313 = F310. (Note: Relative addressing is used only by branch instructions.)

3.1 Description of 6502 Instruction Set

In this section, we describe all of the instructions recognized by the 6502 microprocessor. For each instruction, the following information Is provided:

1. The instruction name—a three letter mnemonic (always capitalized)

2. A description of the operation performed by the instruction.

3. An opcode value for each of the possible addressing modes that can be used with the instruction.

The condition codes in the program-status register that are modified by the instruction.

To form a complete instruction, you first U3e the operation to be performed and the addressing mode desired to select the value of the opcode to be used. The opcode byte is then followed by the (possibly)

additional bytes required by the addressing mode being used.

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