llie mk rocompulet system carties out com-plo\ tasks of the game by performing a large number of simple tasks. Control of the system is the primary tunc lion of the Microprocessor. The Mic roprocessoi causes the system to perform the desired operations hv addressing the Program PKOMs (programmable read-only memories! for an instruction, reading that instruction, then executing the simple task dictated hv that instruction. Temporary storage of data necessary for the execution of a future instruction, sue h as arithmetic operation, takes place in the Page Zero memory.
4.2.1 Program PROMs (bottom of schematic sheet 3):
I he Program PROMs c onsist of read-only memories (ROMs), permanently programmed by Atari to execute the Night Driver game. This memory has the capability of outputting eight bits of data for eac h of 2.048 c ombinations of ones and zeros on the ion address inputs. In computer terminology, this is stated as a memory si/e of 2K x 8.
I he Night Driver game contains one of two combinations of ROM chips to make up the Program PROMs. depending oil when the individual Night Driver PCB was manufactured. For the early produc -lion models. Program PROMs consist of eight c hips las illustrated to the left of the word PROGRAM PROMS on the schematic diagram). Later produc tion models consist of two chips (as illustrated to the right of the word PROGRAM PROMS on tile schematic diagram). I he eight Program PROM chips are c ompletely interchangeable with the two Program PROM chips, but need not be retrofit.
Since data in the Program PROMs is a permanent physic.il configuration of the PROM chips, the data is not lost when power is disconnected from the game or when the i hip is removed from its socket. Since the Program PROMs consist of read-only memories, the resuli of an address input can only be the "reading" of data stored in ihc manufacturing process. It is not possible to "write" in more data. (The term PROM stands tor programmable read-only memory. To Atari, this means thai the chip is a programmable ROM. To you. this c hip is only a ROM.)
4.2.2 Page Zero Memory (right side of schematic sheet 3):
Page Zero memory consists of two random-access memories (RAMsj. Data may be stored in Pago Zero mommy (called "writing" Page Zero), then later rec alled (c ailed "reading" Page Zero). Memory size of Page Zero is 512 x 8.
In order to read Page 7ero. R/VV (pins 16) input of the chips must be a high logic level and OD (pins 9| input musi bo a low logic level. To write Page Zero. R W input must fie a low logic level ancl OD input must be a high logic level.
As previously mentioned, data stored in Page Zero memory is for the purpose of performing operations on data as instructed by the Program
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