Cpu Board

The processor hardware can be broken down into five basic functional blocks as shown in Figure 6-1. The arrows indicate the possible data flow directions between the various blocks. The ALU and Control block are the main components of the processor while the Memory and I/O blocks may be thought of as merely peripherals. Figure 6-2 is a detailed block diagram of the processor. The numbers in each block correspond to the entries in Table 6-1, which lists the IC numbers of the main components of each functional block.

Arcade Cpu Blueprint

Figure 6-1. CPU Functional Block Diagram

The following is a brief description of each block shown in Figure 6-1. The numbers beside each functional block name are the numbers in Figure 6-2 which correspond to a particular function.

The RAM is implemented with three read/write static memories configured as a 256 x 12 bit block. Data can be transferred to or from this memory via the ALU block. The processor uses this RAM as a scratch pad.

The ROM is configured as an 8K x 8 bit block of memory. These memory locations contain the program instructions and/or data. It is accessed via the processor control unit.

The I/O block consists of 8 output lines implemented with a bit addressable latch, 24 input lines implemented with data selectors, and two 12 bit registers which are connected to the X Y display deflection circuits via D/A convertors.

Arithmetic Unit 1,2,3,4,5

The arithmetic unit performs all the arithmetic processing for the system. It consists primarily of two 12 bit accumulators, an arithmetic logic unit and various data selectors. The accumulators can function as temporary storage registers for arithmetic functions upon the data in the accumulators. The data selectors are used to select the various sources of data which will be processed.

The control unit is the heart of the processor. It performs all instruction decoding operations and generates all the necessary control signals which the rest of the hardware requires to function correctly.

The following is a discussion of each block shown in Figure 6-2.

The accumulator selector consists of 3 quad data selectors. They are used to select the output of either the primary or secondary accumulator for processing by various other sections of the systems.

2 & 3 Primary and Secondary Accumulators

The two 12 bit accumulators are implemented with quad bidirectional shift registers. The primary accumulator consists of S4, P4, M4. The secondary accumulator consists of T4, R4, N4. All data manipulation in the processor is accomplished using these two accumulators. All output data flows through these registers.

4. Arithmetic Logic Unit (ALU)

The ALU is used to perform all necessary arithmetic functions within the processor. The ALU is implemented using three 24LS181 (N6M6L6) function generators, three 74LS85 (N9,M9,L9) 4 bit magnitude comparators, and a 74S182 (L4) look ahead carry generator. The data which the ALU manipulates can come from four different sources. The first source is the contents of the accumulators via the accumulator selector. The second and third sources are the ROM and RAM data outputs via the ALU data selector (Nil, Mil, Lll) and the fourth source is the external input selector (E4, D4, C4).

5. Data Selector

The data selector is used to read data into the ALU from either the RAM or ROM memory. Note that the ROM data is only 8 bits wide while the RAM data is 12 bits wide.

6. RAM Storage

The system RAM consists of three 9101C high speed static memory chips connected as a 256 x 12 bit block. The block is 12 bits wide in order to allow the contents of an accumulator to be stored. The processor uses the RAM as temporary storage of program variables, data pointers or any other data of a dynamic nature.

7. RAM Address Selector/Register

13. Line Length Counter

The output of this register is tied directly to the address lines of the RAM. It consists of a multiplexer which routes address data from either the ROM or RAM locations to the RAM address lines. The capability to use RAM data to select RAM addresses is the basis for the indirect addressing mode of the processor.

8. Page Selector

The page selector is used to latch the high order 4 bits of a RAM access instructions.

9. ROM Data Register

The register is used to temporarily hold data from the ROM during an instruction fetch.

10. ROM Memory

The ROM memory consists of the actual memory chips plus a data selector and latch circuit. The latch is used to improve the memory access time during a two byte instruction fetch by allowing one byte of the instruction to be latched while the RAM address lines are decoded for the other byte. The data selector can then be used to rapidly access both bytes of the instruction by switching between the latch and memory outputs.

11. Instruction Register

The instruction register is a latch which holds the current op code as read from ROM. Its output is tied to the instruction decode circuitry which in turn generates the necessary signals to execute the instruction.

12. System Sequencer

The system sequencer is used to decode an instruction op code and to generate the appropriate timed sequence of signals which execute the instruction. The op code is decoded by using it as the address data to a set of decoder ROMS. The outputs of the decoder ROMS are then synchronized with the system clock and used to control the various system functional blocks.

The line length counter is used during the process of drawing a vector to control the length of a vector, by turning off the beam at a pre-determined time after the vector is intiated. The counter is loaded with a value from a line length ROM and then counts up until it overflows which in turn generates a signal to indicate the vector has been finished.

14. Program Address Selector

This selector is used to provide the address data to the program ROM. It selects either the program address counter output or the accumulator selector output and routes this data to the ROM address lines. The ability to use the accumulator contents as address data allows the program to randomly access data tables stored in the ROM or to compute a branch address after a conditional test.

15. Program Address Counter

This is a 12 bit counter whose output defines the next location in ROM to be accessed. It is normally clocked sequentially to step through a program. However, it can be loaded with data from the program address register which is how the jump instructions are implemented.

16. Program Address-Register

This register is a latch used for temporary storage of an address which will be loaded into the program counter during a jump instruction. The input data to this latch can come from either the program ROM or the scratch-pad RAM.

17. Input Selector

The input selector is used to read the state of one of the 24 input lines into the selected accumulator. There are 16 primary inputs and 8 secondary inputs. During an input instruction the upper 11 bits of the accumulator are set to zero while the least significant bit reflects the state of the input line. All input lines have pull up resistors on them so that they will read high if they are left unconnected.

18. Output Selector

19. Display Registers

The output selector is a bit addressable latch used to control the 8 output lines. During an output instruction the selected output line is set to the complement of the least significant bit of the accumulator. The output lines are used to control the audio board, display intensity and the mechanical coin counter.

The display registers are the interface between the processor and the display driver circuits. These registers are latches into which the contents of the accumulators can be stored. The outputs are tied to D/A converters which provide the input voltage to the display deflection amplifiers.

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