The CLK + signal is fed to two division circuits. The first is composed of IC10, IC11, half of IC12, one sixth of IC6, and half of IC28 that form a divide by 126 circuit. The second is composed of IC13 which is a divide by 128 circuit. The signal appearing at IC11-15 is a very narrow positive pulse one-sixtythird the frequencyE of CLK+. IC28 is a "glitch catcher". It's output IC28-2 is a negative going pulse approximately half as wide as IC11-15, and is used to both preset the counters (IC10-9, IC11-9) and feed the divide by two counters (IC12) whose output is a squarewave. IC13 is configured as a simple binary counter whose output frequency (IC13-9) is equal to CLK+ divided by 128. Both counters are enabeled "low" at IC3-12. The outputs of both dividers are fed to the Pot Driver (IC27-2) via a Summing Network consisting of R24, R25, R26 and C15.
Was this article helpful?