In keeping with the progress Exidy has made to satisfy the needs of all those involved with the operation of an Exidy video game, we have duplicated especially pertinent information in both our Operator and Technical manuals. For example, we now are including a complete Parts List and accompanying drawings in both manuals. That way should you need to separate the manuals, the VENTURE™ Technical Manual, Version 2.0, contains all the information a technician needs to service VENTURE™. The Operator's manual, then, contains all information necessary for installation and routine running of VENTURE™.

We have designed the Technical manual to aid in your understanding of schematics. Each board schematic (logic, audio/color, and memory expansion) is accompanied by a description directly opposite it. These are sectioned by the page number of the drawing they describe.

After the board schematic drawings and descriptions, we provide information on Audio Diagnostic Test, Power Supply, Joystick and Audio adjustments. An illustrated parts list follows.

Exidy welcomes your suggestions for more ways to make provide you convenience. Please use our toll free number (800) 538-8402. We'd welcome your ideas.

1. Master Oscillator (ID)

From this oscillator all dynamic operations are derived, such as the processor clock, the main element and line counters, the shift register clocks, as well as all other forms of timing signals.

These components form the final stages of horizontal timing. All operations in this game requiring horizontal positioning or timing have their origin here. Note that, beginning with signal HCLK (from Clock Divide Counter 2D), there are 256 counts prior to setting signal E256 high. When this signal goes high, it indicates that the horizontal blanking period is in progress. At this time the final counter (1E) is preloaded with a higher number than previously loaded. This creates a shorter count the second time around. The shorter count measures the retrace interval. When the retrace count is finished, the counter preloads with a lower number, establishing a longer count sequence again for "real time* sweep of the electron beam across the face of the CRT.

These components form the entire vertical timing operation starting with a clock derived from horizontal timing. These counters count 256 times and then preload with a higher number, causing a shorter count the second time. This shorter count measures the vertical retrace interval. Note that signal L256, when high, indicates vertical blanking is in progress. After the completion of the vertical retrace count, the counters once again preload with a lower number. This way they count 256 times during the sweep of the electron beam down the face of the CRT, allowing the horizontal timers to sweep one complete horizontal line for each count of the vertical counters. Thus, the electron beam reaches the bottom of the CRT, after completing 256 horizontal line sweeps. It then begins the vertical retrace count, and the whole cycle begins anew with the beam starting again at the top of the CRT.

4. Screen J*AM Addresses (7D)

During the time the screen RAM is examined by the logic for output to the monitor screen, addresses must be applied to the screen RAM to count up at a rate corresponding to the image cells conceptually arranged on the screen in a 32 x 32 matrix. The counts used here, 4 from the element counters, and 4 from the line counters, fulfill this timing requirement. The least significant element count used (E8) represents an interval exactly eight times that of one element. The least significant line count used represents an interval exactly eight times that of one horizontal line, or eight times a single line count. Dividing a 256 element line by 8 yields 32, and likewise dividing a 256 line vertical sweep by 8 yields 32. Thus the screen RAM address lines (RAMO through RAM9) count at a rate that creates 32 horizontal counts and 32 vertical counts as the electron beam sweeps the face of the CRT. This makes 1024 conceptual "image cells' into which can then be inserted images of 8 elements by 8 lines. For more information concerning these images, refer to the text for pages 2 and 3 of the Logic Schematics.

5. Coin Input Decoding (1H)

Some models of VENTURE (TM) contain two separate coin inputs for special coinage applications. NOR gatelH combines these separate inputs, making signal 5COINT, which sets the interrupt flip-flop {6E on page 8) when either coin input becomes active, thus forcing the microprocessor to jump to the interrupt service routine. This interrupt driven operation prevents ever missing a coin when inserted. However, this also means that when a game is first powered up, the coin input must be inactive. If for some reason the coin input switch is enabled at the time of power up, the game does not properly initialize until the switch is disabled.

Hardware Generated Line Positioning Proms (3 E, 4E)

These PROMs are not used for VENTURE (TM).

7. Blanking and Video Clocking (5H)

Flip-flop 5H merely combines blanking and all other video.

8. Black and White Composite Video Output (1H)

This circuit is not used for VENTURE (TM). If desired, however, these components may be installed to aid troubleshooting, by acting as a "video probe*.

1. Screen Controller PjiOM (6D)

This PROM controls the direction of data flow into and out of the screen RAM and character generator RAM. It prevents timing errors and buss conflicts, assuring that the microprocessor can write to either the screen or character generator RAM, or read back from either.

The screen RAM is comprised of two 1024 x 4 static RAMs, configured to act as a single 1024 x 8 RAM. This creates a screen matrix of 32 horizontal by 32 vertical positions. A single byte code is stored in each of these positions to represent a particular character. During "real time" (the time the CRT is being swept by the electron beam) these character codes address the character generator RAM.

These character codes, when used as addresses, are combined with the three least significant line counts (LI, L2, L4) to present to the character generator output shift register all the necessary data to form an 8 element wide by 8 line high character on the CRT, located within one of the 1024 positions mentioned immediately above; that is, the 32 horizontal by 32 vertical positions.

The screen, then, is a storage place for single byte codes that call up an 8 x 8 character and place it into the corresponding character cell. This character is stored in the character generator RAM, shown on page 3 of the schematic.

3. Character I mage Storage

Shown on this page are two PROMs (9C, 10C). They could be used as a permanent set of characters. However, VENTURE (TM) uses RAM instead, to increase the flexibility in character manipulation. This portion of RAM appears on page 3 of the Logic schematics.

4. PROM Power and Signal Selection (10B)

This Dip Shunt configures the logic for different types of PROM devices. For VENTURE (TM), however, this Dip Shunt is unnecessary due to the fact that RAM has been used rather than PROM.

5. Character Generator Output Shift Register (12B)

Video from the character generator memory devices (RAM in the case of VENTURE (TM)) is formed by this shift register as a byte of data that displays one line at a time from left to right on the CRT. This ultimately forms an 8 line high by 8 element wide character positioned on the screen according to the time it is presented to the shift register.

Output from this shift register are all the images seen on the screen except the player image and the player missile image.

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