Image Storage MM

1. Character Generator Image Storage RAM (13C, 11C, 14C, 12C)

These four RAMs, when used in this configuration, act as a 2048 x 8 bit RAM. The images placed on the screen are stored in this RAM by the microprocessor, according to the game program. In this RAM images are established, altered, shifted slightly, and even rep Iaced wi th a new set, if required by the program.

When cal led by the logic to do so, the RAM presents, to the character generator shift register, a single byte, representing one line of a particular image. Each image is composed of 8 i ines of data, each line is one byte-wide. Thus, 256 images of 8 x 8 bits can be stored here simultaneously and 'called up* by the screen RAM to be displayed on the CRT in any of the 1024 character eel I posi tions. A single byte code, stored in the screen RAM, calls up a character. The character may change or move by replacing the single byte code in the screen RAM, or by altering the data in the character generator RAM which forms the image.

1. The 6502 Microprocessor (2A)

For detai led information concerning thi s microprocessor, refer to the MOSTEK publication, 6500-10A, MCS Microcomputer Family Hardware Manual.

One feature that should be mentioned here, however, is that this microprocessor has "memory-mapped I/O*. This means that alI ports interfacing to peripherals of any type must be located within the normal memory map, with no duplication of addresses, since no instructions are specifically oriented toward I/O operations.

2* Power-on Reset circuit (connected to 2A pin 40)

When power is first app!ied to a game, a particular sequence of events must occur to set up all logic conditions. If this sequence is broken for whatever reason, the microprocessor may become confused, and the game will not start and run.

This sequence is accomplished when the reset line to the microprocessor is the last I ine a I lowed to reach a "high" logic level. The Power-on reset circuit makes sure this occurs by ut iIi zing the charge time of an RC network as a delay.

If any kind of power interruption occurs during norma! game play, the power-on reset circuit insures that the microprocessor is reset. This alleviates confusing the microprocessor, while it also recreates the original power-on sequence.

3. Processor Workspace R/Vd (4A, 5A)

The RAM, or workspace, consists of the lowest 1024 bytes of memory and can be divided into three separate sections due to distinctly different functions.

The lowest 256 bytes (0 to FF Hexadecimal) is reserved for special software register operations, and is called "zero page*. The processor uses this area to store dynamic variables. For details of this type of operation, refer to 6502 technical literature regarding "Zero Page Addressing".

The next hi gher 256 bytes (100 to 1FF Hex) is reserved for the 6502 stack. The processor stores return addresses in the stack when interrupted or called to execute a subroutine. The game program may also request the processor to store other kinds of information here for later ret r i evaI.

The next higher 512 bytes (200 to 3FF Hex) are used as a scratchpad area. Miscellaneous calculations and their results are temporarily stored here.

4. Main Address Decoding (5C, SD, 5E)

This circuit is the first stage of the address line decoding necessary to organize the memory map; that is, it places specific functions or devices within generalized blocks of the memory map, grouped by function.

For detai Is on the addressing scheme, see MEMORY MAP, Figure 1.

1. Program Memory (6A through 13A)

These memory devices may be 2516, 2716 {5 volt only), or 2732 EPRCMS. If 2516 or 2716 EPRCMS are used, there wi II also be an addi t iona I memory expans ion PCB in use to create more memory space. This PCB is simply an extension of the address, data and control lines present at the merrmy devices situated on the logic PCB.

Note that four of the I ines to eachmerrory device (PCSO through PCS7, PAP19, PAP20, PAP21) are programmable through jumper configurations located at 4B and 11B. This allows different merrory devices to be used and/or facilitates interconnection to the memory expansion PCB {if used).

2, PROM Address Selection (4B, 5B)

This is a second stage of address decoding, used to select each individual memory device when addressed. Signal RQMSEL {from page 4 Main Address Decoding) selects the Program Memory devices in general, and jumper 48, together with decoder 5B further defines an address to a part i cul ar metrory dev i ce.

3. Memory Devi ce 'Personal i ty' SeIec-t ion (11B)

The dip shunt, or junpers block, alters control signal configuration to the programmemory devices. This a I lows the use of alternate size EPRCMS and/or those created by di f ferent manufacturers whose control signal pinouts may not be identical to one another.

1. Moving Object Hor i zonta I (13F, 15F, 14F, 16F)

Counters 13F and 15F form a byte-wide counter which horizontally positions Moving Object 1 on the screen. These counters are preloaded to a certain value by the microprocessor during Vertical Retrace time. Then, after each occurrence of the Horizontal Sync, they begin to count. The count outputs AND'ed through 15E give rise to signal M1H/V, the Horizontal Position Window for Moving Object 1. Counters 14F and 16F are the equivalent circuit for Moving Object 2.

2. Movi ng Object Vert ical Pos i t i on Counters (16E, 12E, 1E, 13E)

Counters 16E and 12E form a byte-wide counter which positions Moving Object 1 vertically on the screen. These counters are preloaded to a certain value by the microprocessor during Vertical Retrace time. Then, after each occurrence of Vertical sync, they begin counting. The four count outputs of the least significant of these two counters (M1L1, M1L2, M1L3, M1L4) are sent to the moving object image PROM to speci fy which line of the image is presently being displayed. The AND'ed outputs of the second counter give rise to signal M1\W, the Vertical Position Window for Moving Object 1. Counters 11E and 13E are the equivalent circuit for Moving Object 2.

3. 'Write Moving Object' Cfecoding (6F, 16H, 5E, 3F)

Consists of two distinctly different functions. 6F and 16H form the circuit that generates the load pulses for the moving object position counters, while 5E and 3F simply prevent the counters from counting during blanking.

4. Color Interface Output (16B)

This is a 14 pin DIP socket used as the connector interface to the color selection circuitry, located on the audio PCB. The signals and their functions are listed below:

Pin #

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