Steering Board 00906003 B

hA/V

Figure 4-12 Video Interface 1 (Part of Game PCB 030845-:

Circuitry -XX A)

a. video interface circuitry

There are two sections of the video circuit. The playfield circuit produces the flippers, drop targets, thumper bumper lights, and all video messages The ball circuit produces the ball image.

Playfield Circuit

Playfield video is produced by a process known as DMA (direct memory access). DMA is a term used to describe the circuitry, peripheral to the MPU, which temporarily takes control of the address and data bus to gain direct access to a portion of the MPU's RAM memory.

The MPU stores data into the playfield RAM during the write cycle (B<t> 2 and WRITE are both low). When BO 2 goes high, the DMA addresses the playfield RAM with horizontal and vertical sync signals (see chips F2 and H3

in Figure 4-6). In other words, the MPU writes information into the RAM that defines the playfield picture, then sync extracts the information from the RAM at the time it is actually displayed -

The monitor display is subdivided into small rectangles called "stamps". Each "stamp" is eight bits wide by eight lines high Stamps are a convenient way for the MPU to assemble a playfield picture with a minimum of data.

The playfield circuit, when clocked by horizontal sync component 4H, latches the RAM data at the output of C4. Five bits of the latched data directly address the playfield picture ROMs C5 and D5. Vertical sync components IV, 2V and 4V are Exclusive ORed with 2Q of latch C4. The outputs of the three Exclusive ORs become the three lower-order address inputs of the playfield picture ROMs. If RAM D6 is high, then these Exclusive ORs invert IV. 2\I and 4V. and the stamp is read out upside down. If RAM D6 is low, IV. 2V, and 4V are not inverted, and the stamp is scanned in its normal sequence. Therefore, the six RAM data bits RAMDO thru

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